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My PhD is officially complete. The final doctoral defense took place today and I can thankfully say that I passed with flying colors. The dissertation is titled Tunable Mismatch Shaping for Bandpass Delta-Sigma Data Converters. I’m looking forward to a long summer of rest, particularly after the intensity of the past several months.

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The final doctoral defense for my PhD has been scheduled for 1 PM on April 20, 2011, taking place in ACE 2.404B on-campus at the University of Texas. My dissertation is titled Tunable Mismatch Shaping for Bandpass Delta-Sigma Data Converters.

From the abstract:

Oversampled digital-to-analog converters typically employ an array of unit elements to drive out the analog signal. Manufacturing defects can create errors due to mismatch between the unit elements, leading to a sharp reduction in the effective dynamic range through the converter. Mismatch noise shaping is an established technique for alleviating these effects, but usually anchors the signal band to a fixed frequency location. In order to extend these advantages to tunable applications, this work explores a series of techniques that allow the suppression band of the mismatch noise shaping function to have an adjustable center frequency. The proposed techniques are implemented in hardware and evaluated according to mismatch shaping performance, latency and hardware complexity.

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Today, I presented a guest lecture to a class of graduate students at the University of Texas at Austin. The topic was Parallel Sorting Networks, and covered material from the seminal Introduction to Algorithms, by Cormen Leiserson and Rivest.

The problem statement: How can a random selection of N numbers be sorted in sub-linear time? Sorting is indeed a well-known problem, and there exist numerous algorithms and implementations in serially-computed software instructions. However, a sorting network is a comparison network in which multiple comparisons can be performed in parallel. The aim of the lecture was to provide a methodical construction of parallel sorting networks in hardware.

There are few assumptions on the input to such a network, consisting of N arbitrarily-ordered numbers which can be compared to one another. The expected output is a list of N numbers in a positionally-sorted order, where the sorting direction can be set to either ascending or descending order. N is assumed to be a power-of-2, but the techniques can be extended to non-power-of-2.

Besides the functional goal above, there is an efficiency goal to reduce the network complexity, i.e. number of comparisons, whilst maintaining a shallow network depth from input to output. In hardware terms, this translates to maintaining low hardware complexity whilst shortening the latency through the network. Low latency is particularly important for stability when such a system is used within an automatic feedback loop.

Chapter 28 in the aforementioned textbook on Algorithms covers this topic extremely well. The authors present a step-by-step approach to solving this problem and provide some good references. Parallel sorting is an old topic, and has been covered as far back as Donald Knuth‘s Sorting and Searching chapter in Volume 3 of The Art of Computer Programming from 1973, and further. There will likely never be an end to applications for these methods.

I concluded the talk with an application example that is very relevant to my current research. A fast and small parallel sorting network is needed within the vector quantizer of a vector-based mismatch shaper. In this case, the vector quantizer is used within the feedback loop of a Delta-Sigma data converter.

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The proposal went great! I’m now officially a PhD candidate. Embarking on a journey countless others have undertaken, I now begin a tireless battle to push to the end (and not necessarily the logical conclusion) through the setbacks, the self-indulgence and self-restraint, the lapses of discipline and manic exertions thereof, and all the while squirming through the ever-tightening grip of despair in hopes of feeling the dizzying heights of discovery.

Challenge accepted!

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The proposal for my PhD qualification has been scheduled for 8:30 AM on October 14, 2008, taking place in ACE 3.408 on-campus at the University of Texas. The dissertation is tentatively titled Tunable N-Path Mismatch Shaping for Bandpass Delta-Sigma Modulators.

From the abstract:

In a unit-element digital-to-analog converter (DAC) used within a Delta-Sigma converter, mismatch noise can sharply reduce the achievable signal-to-noise ratio (SNR). Mismatch noise-shaping is an established technique for spectrally shaping the noise power created by mismatch-error in order for most of it to fall outside the signal band. This is done by dynamically re-arranging the order in which quantizer unit-elements are utilized. This research proposes a mismatch noise-shaping technique that allows the center frequency of the mismatch noise transfer function to follow the center frequency of a tunable bandpass Delta-Sigma modulator.

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